In general, a semiconductor test device (LSI tester) for performing a function test of an LSI inputs a predetermined test pattern signal into an LSI to be measured which is a device under test (DUT), compares output data output from the LSI to be measured with a predetermined expected value pattern signal, judges agreement/disagreement, and accordingly detects/judges whether or not the LSI to be measured is satisfactory.
FIG. 6 is a block diagram showing a schematic constitution of a conventional general semiconductor test device.
As shown in the figure, a conventional LSI tester (semiconductor test device) 110 has: a level comparator 113 which compares a level of output data of the LSI to be measured (DUT) 101 with that of a comparison voltage; a pattern comparison unit 114 which compares the output data of the LSI to be measured 101 with a predetermined expected value; a flip-flop 121 for inputting the output data of the LSI to be measured 101 into the pattern comparison unit 114 at a predetermined timing.
In the conventional semiconductor test device constituted in this manner, first a predetermined test pattern signal is input into the LSI to be measured 101 from a pattern generation unit (not shown), and a predetermined signal is output as output data from the LSI to be measured 101. The output data output from the LSI to be measured 101 is input into the level comparator 113 of the LSI tester 110. The output data input into the level comparator 113 is compared with the level of the comparison voltage, and output to the flip-flop 121.
In the flip-flop 121, a signal from the level comparator 113 is held as input data, a strobe from a timing generation unit (not shown) is used as a clock signal, and output data is output at a predetermined timing. The output data output from the flip-flop 121 is input into the pattern comparison unit 114, and compared with a predetermined expected value data output from a pattern generation unit in the tester, and a comparison result is output.
Moreover, from this comparison result, it is detected whether or not the output data agrees with the expected value, and it is judged whether or not the LSI to be measured is satisfactory (Pass/Fail).
In this manner, in the conventional semiconductor test device (LSI tester), the output data output from the LSI to be measured is acquired at the timing of the strobe output at a predetermined timing in the tester, and this strobe has been a timing signal output from the timing generation unit disposed independently of the LSI to be measured. Additionally, in the conventional semiconductor test device which acquires the output data of the LSI to be measured by an independent timing signal output from this tester in this manner, there has occurred a problem that the test LSI device in which the clock is multiplexed onto the output data and output cannot be tested.
In recent years, speeding-up of the LSI has remarkably proceeded, and to speed up data transfer, a new LSI device represented by a serializer and deserializer (SERDES) or the like has been provided. The SERDES is an LSI device which converts parallel data into serial data or the serial data into the parallel data, a high-rate data transfer is possible, and the device is used as an interface or the like of data communication. Moreover, in the LSI such as the SERDES, for example, when the parallel data is converted into the serial data and output, the clock is multiplexed onto the output data in the LSI, and the output data is output at an edge timing of the multiplexed clock.
Therefore, to perform the test of the LSI device in which the clock is multiplexed onto the output data in this manner, the output data to be compared with the expected value data needs to be acquired at the timing of the multiplexed clock. However, in the conventional semiconductor test device, as described above, since the output data output from the LSI to be measured is acquired by the timing signal output from the timing generation unit independent of the LSI to be measured, it has been impossible to acquire the output data at the timing of the clock of the LSI to be measured.
Therefore, in the conventional semiconductor test device, it has been impossible to correctly test the LSI of the clock/data multiplexed type from which the output data with the clock multiplexed thereon is output.
Here, as a method of testing the LSI in which the clock is multiplexed onto the data, as in an LSI tester 210 shown in FIG. 7, it is considered that a test terminal (“CKO” shown in the figure) for outputting the clock, separate from an output terminal of the output data (“Q” shown in the figure), is disposed in an LSI to be measured (DUT) 201 into which a test signal is input from a pattern generator (PG) 211 via a waveform forming unit (format controller: FC) 212, and a clock signal is output from this test terminal, and input into a pattern comparison unit (digital compare: DC) 214, a fail analysis memory (data failure memory: DFM) 215 and the like.
However, when the test terminal for the clock output, which has not been originally disposed, is disposed in the LSI to be measured in this manner, a device constitution is changed for the test, the number of pins increases by the test terminal for use only in the test, and it has been actually difficult to adopt the terminal.
Moreover, in the output data output from the LSI to be measured, for example, a signal becomes HIGH (or LOW) over two or more clock cycles, the signal does not necessarily change at the edge timing of the clock, and an operation waveform is not the same as that of the multiplexed clock. Therefore, when the output data is simply acquired, it is difficult to correctly retrieve the edge timing of the multiplexed clock, and the output data cannot be synchronized with the clock at a correct timing.
That is, to perform the test using the clock multiplexed onto the output data, it is necessary to dispose a certain function (source synchronous function) for synchronizing the multiplexed clock with the edge timing of the output data. When the terminal for outputting the clock is simply disposed in the LSI to be measured to output the clock as shown in FIG. 7, the clock/data multiplexed type LSI cannot be correctly tested.
Furthermore, the clock output from the LSI to be measured generally has a jitter (irregular fluctuation of the timing), and the edge timing fluctuates by the jitter. Therefore, when the test terminal is simply disposed to take out the clock, the output data is taken in at the timing of the clock which has fluctuated by the jitter, and there has also been a problem that a correct test result cannot be obtained.
In the method in which the test terminal for outputting the clock is disposed in the LSI to be measured in this manner, it has been impossible to test a clock/data multiplexed type LSI such as SERDES in which the clock is multiplexed onto the output data.
The present invention has been proposed in order to solve the above-described problem of the conventional technique, and an object thereof is to provide a semiconductor test device comprising a clock recovery circuit having a source synchronous function capable of taking a multiplexed clock signal from output data of an LSI to be measured to adequately correct an edge timing of the clock signal while synchronizing the output data, so that the clock signal multiplexed onto the output data can be easily and securely acquired without using any timing signal from the outside or without disposing any extra output terminal or the like in the LSI to be measured, and the output data of the LSI to be measured can be correctly retrieved by a recovery clock corrected at a proper edge timing.